are diff and sdiff on linux?
"drivers" somewhere. in big title? in context of no OS
instructions can take multiple cycles to complete
integrated circuits + Very Large Scale Integration + Metal Oxide Semiconductor (MOS) chips
manufacturing CPUs: + overclocking/cpu scaling + ram hz?
pipeline model for CPU bubbles in cpu? related to pipeline model.
in title: pipeline, instruction level parallel, superscalar, microcode/firmware
Super scaler processor: can do multiple operations per cycle by having multiple execution units. Separate concept to multiple cores
+ something on cache * SRAM (stochastic random-access memory) as opposed to DRAM (dynamic access memory) which is regular ram * part of the CPU in practice * in between register and DRAM
Will a conditional jump be taken?
Predict where to go next
cpu out of order execution
cache branch prediction
Data (SIMD) (RV64IMFDQV_Ziscr_Zifencei) and Basic Linear Algebra Subprograms (BLAS) (computerInstructions) int ALU: multiplier-accumulator (MAC) + does this belong in mult section or not? + i think this is part of P, not part of standard multiply anyway
rv32im with multiplication and division
rv32imf with float
floating ALU: fused multiply-add (FMA) + system on a chip + SSE/AVX + Microcode
on floating, include RV64IMF
cisc: + When discussing cisc, discuss "register memory" as alternative to "Load store". "CISC and the register-memory architecture"? + register memory architecture allows operations on memory as well as registers
op codes can take many clocks built from simpler instructions + actually this applies to risc too. point is other things right? different instruction lengths, direct RAM access in operations
FOR BELOW. ARE ARCHITECTURES FEATURES OF A CPU INSTRUCTION SET, OR FEATURES OF ITS IMPLEMENTATION? impacts where this should go. + these are about implementation, so later
concepts of different architecutes: + harvard architecture: separate buses for data and code (and possibly different memory too) (these are data bus and address bus) + von neumann: single bus for both, same memory + data bus and address bus, but on same memory
psu notes atx 20+4 main power cable. 20 on older/lower power motherboards + aka p1, pc main, atx cable + powers motherboard, ram, notably not CPU. 20+4 cable means can go with either 24 or 20 motherboard pci e power cables are not symettric. only one end will fit in PSU. + 6 or 8 pin. 6+2 cables can be used. + GPUs use pci e. + not all pci e devices need extra power, eg wireless card. GPUs generally do. modular vs non-modular PSU cpu connector on motherboard. either 4 or 8 pin. 4+4 cable allows for flexibility. + aka p4, eps connector. 12V other power: sata cable. required for sata, but can also be used for eg rgb lights. 6pin
dram: row hammer attack
h3 on validating CPUs in big page on manufacturing CPUs in perihperals: concept of memory mapped IO. parts of CPU: branch unit; dispatch unit microarchitecture: the way an instruction set architecture is implemented. could ave differnet microarchitecture for the same ISA Load store unit as specialised execution unit
manufuacturing cpus and perihperals: thign on io bus